In the field of semiconductor device manufacturing, active semiconductor devices such as, for example, transistors are normally manufactured by well-known front end of line (FEOL) technologies. Following the formation of active devices, interconnects or interconnect structures (as the terms may be used interchangeably throughout this application) may be formed or created using well-known back end of line (BEOL) technologies. An interconnect may include for example trenches and/or vias, made of conductive and/or metal materials, and may be used to selectively connect a set of active devices to achieve a desired function or performance or a combination thereof. In addition, two or more layers of interconnect structures may be formed together, creating an interconnect block, referred to herein as an interconnect unit.
Conventionally, an interconnect structure or a layer of interconnect structure may be formed by first creating one or more via openings in a layer of ILD materials. The ILD layer may be formed or deposited, such as through a conventional CVD or MOCVD technique as well-known in the art, on a surface of a prior level of interconnect layer or interconnect structure. Subsequently, one or more trench openings may be created in the same ILD layer, in regions or areas where at least one or more of the via openings have been created. The trench openings may therefore overlap at least partially with the via openings. Following the formation of the structure of via and trench openings but before filling of the opening with certain types of conductive materials, a layer of liner, which may be a metal liner, may be deposited onto the bottom and/or to the sidewalls of the opening in the ILD layer. As is well-known in the art, the liner may be deposited to reduce and/or prevent possible diffusion of a conductive material, which fills up the via and trench opening in a follow-up step, into the ILD material for example during the manufacturing of the interconnect structure. Such diffusion of conductive metal materials into the ILD layer may cause device shortage and performance degradation, among others.
Conventionally, the metal liner may be deposited with a thickness that is sufficient to provide a relatively good coverage for the via openings. However, the metal liner in the trench region, which is deposited at the same time as that in the via region and thus having a thickness being dictated by the thickness of the metal liner deposited in the via region, may be unnecessarily thicker than it needs to be because a trench usually requires less liner coverage, as is known in the art. Consequently, a thicker metal liner in the trench region, coupled with a relatively low conductivity of the liner material, may cause an overall high resistance of the metal line formed later in the trench region.
In addition to possible high resistance, it is also well-known in the art that the conventional process of forming interconnect structures, as described above, may cause trenches or metal lines to have roughened trench bottoms. The roughness at the bottom of trench is known, as described below in detail, to be caused by performing via gouging before applying the metal liner to the via and trench openings. This roughness becomes particularly severe when a layer of ultra-low dielectric k-constant (ULK) material is used as the ILD layer. A roughened trench bottom may result in device performance degradation such as, for example, increased resistance and possible shortage with neighboring active devices, and in severe cases may force the trench to be formed with less depth.
Therefore, there exists a need in the art to tailor the thickness of the liner used in the trench region and in the via region during the formation of the interconnect structure and so to achieve better device performance. There is also a need for the mitigation of roughness at the bottom of trenches caused by the above conventional process during formation of the interconnect structure.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for purpose of clarity.